Product details
Product Overview
The RFSPA1249C-1113P35 is a GaN power amplifier chip covering 11–13 GHz, with 22.5 dB power gain, 45.5 dBm saturated output power and 37% PAE. It operates in both pulsed and CW modes. Chip size: 5.77 × 6.70 × 0.10 mm. All chips are 100% DC and RF tested on-wafer.
Key Features
11–13 GHz bandwidth
22.5 dB power gain with ±0.5 dB flatness; 28 dB linear gain
45.5 dBm saturated output power
37% power-added efficiency (PAE)
IMD3 −25 dBc @ Pout = 43 dBm (two-tone spacing 5 MHz)
Operates in both pulsed and CW modes; 100% DC and RF tested on-wafer
Technical Specifications
| Model | RFSPA1249C-1113P35 |
|---|---|
| Product Category | MMIC Products |
| Device Type | GaN MMIC Power Amplifier Chip (bare die) |
| Frequency Range | 11–13 GHz |
| Linear Gain | 28 dB (typ) · flatness ±1 dB |
| Power Gain | 22.5 dB (typ) · flatness ±0.5 dB |
| Input / Output Return Loss | −7 dB / −9 dB |
| Saturated Output Power | 45.5 dBm (typ) |
| PAE | 37% (typ) |
| IMD3 | −25 dBc @ Pout = 43 dBm, two-tone spacing 5 MHz |
| Operating Current | 3.7 A (typ) · +28 V @ 0.8 A (quiescent) |
| Chip Size | 5.77 × 6.70 × 0.10 mm |
| Thermal Resistance | 1.3 °C/W |
| Operating Modes | Pulsed and CW |
| Test Conditions | VD = 28 V (CW), VG = −2.8 V, Pin = 23 dBm, TA = +25 °C |
| Absolute Maximum Ratings | VDS +32 V · VGS −5 V · Pin +30 dBm · Tch +200 °C |
| RF / Bias Pads | RF_IN / RF_OUT: 100 × 120 μm² · VG: 120 × 100 μm² · VD1: 150 × 100 μm², VD2: 140 × 100 μm², VD3: 150 × 110 μm² · outline tolerance ±20 μm |
Assembly & Handling Notes
Store in a dry, clean N2 environment; the 6H-SiC substrate is brittle — handle carefully to avoid damage
Carrier CTE should be close to 6H-SiC (4.2×10⁻⁶/°C); CuMoCu, CuMo or CuW recommended; avoid voids between chip and carrier and ensure good heat dissipation
Eutectic bonding with AuSn solder (Au:Sn = 80%:20%), temperature ≤300 °C, time ≤30 s; avoid rapid temperature changes
Gold wires of 25–30 μm diameter recommended; bonding stage temperature ≤250 °C
Power sequencing: apply gate bias before drain bias on power-up; remove drain bias before gate bias on power-down
External capacitors C1 = 100 pF, C2 = 1000 pF close to the chip (within 500 μm); DC-blocking capacitors integrated at chip input and output
ESD precautions: wear a grounded anti-static wrist strap and ensure the sintering/bonding stages are well grounded
